CENTRIFUGEControl architecture
Design review

01 / Overall system

Centrifuge Control Architecture

One supervisor coordinates the machine, display, drive, and records.

Interface and sensingDrive and outputs

Optional: two I2C buses (+2 GPIOs); see view 04.

RS485 / 1Ethernet / Wi-FiGPIO / pulsesRS485 / 2GPIO / driverNative USBSDA / SCL
PROTECTIONIndependent path to be defined

Blocks show logical connections.
Carrier routing and GPIOs remain provisional.

RS485NetworkI2CDirect I/O / USB
Select a block to inspect its interfaces
Architecture review · 19 October 202602 RS485 links · Datasoft over Ethernet or Wi-Fi

02 / Machine interface

Machine inputs and lid control

Four inputs reach the supervisor directly. One output commands the lid-lock driver.

Status inputFault inputInterrupt / countInterrupt / timing DO / driver

Lid status does not yet establish separate lock-engaged feedback.

INTERFACE BOUNDARYThe five signals were identified as motor-board I/O. Existing conditioning, driver placement, and connector routing need confirmation.
2 status inputs + 2 pulse inputs + 1 output = 5 GPIOsSignal levels, edge rates, and fault behaviour remain open

03 / Communications

Two serial links and one network client

The display and VFD use separate RS485 ports. Datasoft connects over Ethernet or Wi-Fi.

RS485 / 1RS485 / 2Ethernet
Datasoft transport

Ethernet path shown through the board's W5500. This selector illustrates the architecture.

One UART remains available

Two of the ESP32-S3's three UARTs serve RS485. Debug use still requires GPIO allocation.

TO DEFINEBaud rates, transceivers, termination, isolation, and loss-of-link behaviour. RS485 does not establish Modbus RTU.
Conventional RS485 allocation: 2 × (TX + RX + direction) = 6 GPIOsDatasoft application protocol remains open

04 / Measurement and persistence

A shared I2C bus and one NOR flash

RTD acquisition, parameter storage, and timekeeping use separate I2C devices.

Proposed ESP32-S3-ETH board
AnalogSDA / SCLI2C busThree devices
Two shared signals Existing SPI flash interface
Distinct I2C addresses and compatible electrical requirements are requiredmicroSD retention remains an open storage decision

05 / Integration status

GPIO budget and remaining decisions

The identified interfaces fit the count. Supporting controls and final wiring still need allocation.

Conventional RS485 direction control
13 / 15 GPIOs
Two pins remain before debug and supporting controls.
5 Machine I/O2 Shared I2C6 Two RS485 ports2 Not yet assigned

The count excludes debug, additional drive-enable/interlock signals, watchdog, USB power control/status, and peripheral interrupt lines. Ethernet, native USB, and onboard NOR use existing board connections.

Automatic-direction option: 11 GPIOs for the identified functions if both ESP32-side RS485 transceivers support a validated automatic-direction circuit.

Open interface decisions

  1. 01

    VFD and display protocols

    Command/status mapping, serial parameters, and link-loss response.

  2. 02

    Machine signal characteristics

    Logic levels, solenoid polarity, pulse rates, and Hall identification tolerances.

  3. 03

    Measurement and persistence

    RTD circuit, I2C parts/addresses, flash partitions, and microSD requirement.

  4. 04

    Networking and USB host integration

    Datasoft application protocol, protected VBUS, and concurrent operation.

Independent protection

Protection circuitry and release conditions remain to be defined. The application diagram is not a released wiring or safety design.

Independent protective path
Architecture to be defined
Drive inhibition
Safe lid-release gating
Source: current architecture and I/O requirementsPin allocation pending · Hardware validation pending

I/O requirements ↗

Design record

Notes and sources

This presentation follows the latest project decisions: two RS485 links, Datasoft over Ethernet or Wi-Fi, and one onboard Winbond NOR device.

Keyboard: Left/Right to navigate, Home/End for first/last view, 1–5 to jump, F for fullscreen, A for reading mode, P to print, and Escape to close details.