# ESP32 interface requirements

The user supplied this interface list on 19 October 2026 and subsequently confirmed one Winbond NOR flash device, RS485 communication with the VFD, and Datasoft communication over Ethernet or Wi-Fi. Two RS485 ports are required: display and VFD. This replaces the earlier assumptions about the HMI UART connection, PC gateway, rotor identification, and temperature channels. The ESP32-S3-ETH remains a proposed controller; its previous pin allocation must be revised for this list.

## Identified interfaces

Directions are relative to the ESP32. The first five signals belong to the interface described by the user as the motor drive board I/O; their connector routing and existing signal conditioning still need definition.

| Function | ESP32 interface | Requirement or open detail |
| --- | --- | --- |
| Lid status | Digital input | Establish logic level, polarity, and whether it reports closure or locking |
| Rotor imbalance | Digital input | Establish logic level, polarity, and fault indication |
| Lid lock solenoid | Digital output to driver | Confirm existing driver location, command polarity, coil requirements, and power-loss behavior |
| Tacho sensor | Direct pulse input with interrupts | RPM measurement by pulse counting; pulses per revolution and maximum pulse rate required |
| Rotor identification Hall sensor | Separate direct pulse input with interrupts | Determine angular spacing between two magnets; magnet pattern and identification tolerances required |
| RTD temperature measurement | 16-bit ADC on I2C | ADC part, RTD type, wire configuration, channel count, excitation, and accuracy remain open |
| External parameter memory | I2C non-volatile memory | Part, address, capacity, endurance, and write frequency remain open |
| RTCC | I2C real-time clock/calendar | Part, address, backup supply, and time-setting behavior remain open |
| Winbond NOR flash | SPI flash interface | One device total; use the proposed board's existing W25Q128 for firmware and allocated data storage |
| Ethernet | Board Ethernet interface | Proposed ESP32-S3-ETH uses onboard W5500 over SPI |
| USB | Native USB interface | Earlier USB export requirement implies host operation; connector and VBUS implementation remain open |
| Waveshare display | Dedicated RS485 port | ESP32-side transceiver and protocol required |
| Datasoft | Ethernet or Wi-Fi | No RS485 port; define application protocol, connection settings, access permissions, and reconnect behavior |
| VFD | Second dedicated RS485 port | Confirm drive model, protocol, command/status mapping, baud rate, and communication-loss behavior |

This identifies **four digital inputs, including two pulse inputs, and one digital output**, plus three I2C device functions, one NOR flash device, Ethernet, Wi-Fi, USB, and **two separate RS485 ports**. Datasoft uses the existing Ethernet or Wi-Fi connection. The VFD uses RS485; its supported run/stop, speed-reference, and status commands must be established from the drive documentation.

## Changes from the earlier allocation

- The display link is RS485. Datasoft communicates with the ESP32 over Ethernet or Wi-Fi; its previous RS485 port and the earlier display-based PC gateway are superseded.
- The second independent RS485 port connects to the VFD. RS485 specifies the electrical interface; Modbus RTU or another protocol is not yet confirmed.
- Rotor identification uses a Hall pulse signal. The earlier tentative four-bit expander allocation does not implement this requirement.
- Keep the command named **lid lock** until the mechanism establishes its polarity. The earlier label **lid unlock** must not determine wiring or firmware behavior.
- Separate lock-engaged feedback, drive permit, and watchdog signals were earlier proposals; they are not confirmed by this list. Their need remains part of the protection/interface review.
- The RTD ADC and external parameter memory are separate I2C functions. ADS1115 and DS3231 remain earlier candidates, not confirmed component selections. The previous assumption of two temperature channels is superseded.
- Retaining microSD alongside NOR flash is unresolved; NOR must not silently replace or duplicate the earlier storage requirement.
- Count the onboard W25Q128 as the single Winbond NOR device for the proposed board. No second NOR chip or additional application GPIO allocation for flash is planned. External I2C parameter memory remains a separate requirement.

## Resource implications

The three I2C functions can share SDA/SCL if their addresses and electrical requirements permit. Additional ready, interrupt, write-protect, or alarm signals are not yet allocated.

For two independent half-duplex RS485 ports, a conventional arrangement uses two UARTs and six ESP32 signals: TX, RX, and direction control per port. Validated automatic-direction transceivers on both ESP32-side interfaces could reduce that to four; this is an option, not the selected circuit. The ESP32-S3 has three UART controllers, so one remains available for debugging or another use, subject to GPIO allocation. Debug pins are not included in the budget below. See [Espressif UART documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/peripherals/uart.html).

Using the earlier board restrictions, there are 15 candidate exposed GPIOs. The revised budget is:

| Function | Conventional direction control | Automatic direction on both ports |
| --- | ---: | ---: |
| Four digital inputs and one digital output | 5 | 5 |
| Shared I2C SDA/SCL | 2 | 2 |
| Two RS485 ports | 6 | 4 |
| Additional application GPIOs for onboard NOR | 0 | 0 |
| Total | **13** | **11** |
| Margin against 15 candidate exposed GPIOs | **2 remaining** | **4 remaining** |

Ethernet and native USB use the board's already-reserved pins; Datasoft uses Ethernet or Wi-Fi without a dedicated serial interface. The totals exclude debug pins and any additional drive-enable/interlock signals, watchdog, USB power-control/status pins, or peripheral interrupt lines. The identified interfaces fit the 15-pin count with conventional direction control, leaving two pins before those supporting functions. This removes the previous one-pin shortfall; a complete assignment and hardware validation are still required. Automatic direction or expansion remains optional if further signals are needed.

The proposed board already contains W25Q128 program/data flash, according to the [Waveshare board documentation](https://docs.waveshare.com/ESP32-S3-ETH). Its 16 MB capacity is shared between firmware, any update slots, and data partitions; it is not all free application storage. Establish the partition layout, retention, and write workload before committing storage capacity. Native USB debugging must not be assumed available while the same interface serves USB host export.

## Measurement and integration checks

- Keep tacho and Hall inputs on direct ESP32 pins. Define edge selection, pulse widths, filtering, and maximum event rates before choosing interrupt handling. Hardware capture with interrupt callbacks is also available; see [Espressif capture documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/peripherals/mcpwm.html).
- Hall pulse timing alone is not a speed-independent angle measurement. Under approximately constant speed, angular separation is `360 × inter-magnet interval / revolution period`. Define how the revolution period and magnet pair are identified, including complementary intervals, acceleration, and missing pulses.
- A 16-bit ADC requirement does not specify RTD measurement accuracy. Establish the analog circuit, reference/excitation, lead compensation, calibration, and sensor-fault detection before selecting the ADC.
- Establish the VFD protocol and command/status mapping, and distinguish lid closure from confirmed locking before freezing the allocation. Independent drive inhibition and release conditions remain separate design work.