# Centrifuge pin assignment revision status

**The allocation below is superseded.** The user's revised [I/O requirements](io-requirements.md) specify two separate RS485 ports for the display and VFD, Datasoft over Ethernet or Wi-Fi, a Hall pulse input for rotor identification, a lid-lock command, an RTD ADC, I2C parameter memory, RTCC, and one Winbond NOR device. The old map and `data/gpio-assignment.csv` do not allocate this combination and must not be used as the current wiring plan.

The VFD communication interface is RS485, and the proposed board's existing W25Q128 is the single planned NOR device. VFD protocol details and serial direction-control circuits remain open. The current conventional allocation needs 13 application GPIOs against 15 candidate exposed pins, leaving two before debug and supporting controls; a complete assignment remains necessary. `data/i2c-devices.csv` likewise preserves earlier candidates; its temperature-channel and expansion assumptions are not the current requirement. Board reservations below remain inputs to the revision, subject to the exact hardware used.

## Earlier allocation retained for reference

This allocation is for the **Waveshare ESP32-S3-ETH standard board, SKU 28972**, paired with the RP2350-Touch-LCD-7. It assumes an RS485 motor controller, two temperature channels, lid closed and lock engaged switches, a digital imbalance signal, and a tachometer pulse signal. The final machine inventory is still outstanding.

**Result:** this assumed configuration fits with a small interface carrier and I2C expansion. Fourteen application GPIOs plus one debug TX consume all 15 suitable exposed pins in this allocation. Additional direct inputs, precise capture signals, or interfaces may require a revised board choice or allocation.

## Supervisor GPIO allocation

Directions below are relative to the ESP32. Header positions refer to the Waveshare 40-position board pinout orientation, not chip pad numbers or individual connector numbering. Verify orientation against the [local pinout image](../research/ESP32-S3-ETH-pinout.webp) before wiring.

| Function | GPIO | Header position | Direction | Connection or condition |
| --- | ---: | ---: | --- | --- |
| HMI UART1 TX | 1 | 25 | Output | To RP2350 GPIO17 RX |
| HMI UART1 RX | 2 | 26 | Input | From RP2350 GPIO16 TX |
| Motor UART2 TX | 15 | 29 | Output | To RS485 transceiver DI |
| Motor UART2 RX | 16 | 32 | Input | From RS485 transceiver RO |
| Motor RS485 direction | 17 | 34 | Output | Transceiver DE and active-low RE arrangement to be finalized |
| I2C SDA | 18 | 31 | Bidirectional | Local expansion bus |
| I2C SCL | 38 | 14 | Output | Local expansion bus |
| Lid closed | 39 | 12 | Input | Conditioned switch signal |
| Lock engaged | 40 | 11 | Input | Conditioned feedback signal |
| Digital imbalance | 41 | 10 | Input | Conditioned digital indication |
| Tachometer pulse | 42 | 9 | Input | Conditioned speed pulse signal |
| Drive permit request | 47 | 5 | Output | Hardware-gated request with safe inactive default |
| Lid unlock request | 48 | 4 | Output | Driver and independent safe-release gating |
| External watchdog heartbeat | 44 | 22 | Output | External watchdog circuit; disable UART0 receive on this pin |
| UART0 debug TX only | 43 | 21 | Output | Debug receive adapter; no UART0 RX allocated |

GPIO39–42 are also external JTAG pins. This plan repurposes them and therefore does not retain JTAG on those pins. Native USB debugging cannot be assumed to remain available while the same native USB interface is serving a flash drive.

If the motor controller instead uses CAN, GPIO15/16 could be reassigned to the controller's CAN TX/RX functions through an appropriate transceiver, potentially freeing GPIO17. This is an alternative pending confirmation, not the present wiring plan. PWM, analog control, or extra motor feedback would require another review.

## Onboard pin reservations

| Use or restriction | GPIOs | Treatment |
| --- | --- | --- |
| W5500 Ethernet | 11 MOSI, 12 MISO, 13 SCLK, 14 CS, 10 INT, 9 reset | Reserved; proposed SPI2 |
| microSD | 6 MOSI, 5 MISO, 7 SCLK, 4 CS | Reserved; proposed separate SPI3 |
| Native USB | 19 D−, 20 D+ | Reserved for USB function |
| RGB LED | 21 | Reserved for onboard LED |
| Camera power enable | 8 | No camera in this configuration; leave disabled |
| Flash and PSRAM | 26–37 | Unavailable or excluded from application use |
| Strapping pins | 0, 3, 45, 46 | Excluded from this baseline |

GPIO33–37 appear on the header, but the R8 device uses them for octal PSRAM. Do not count them as expansion pins. See the [ESP32-S3 GPIO documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32s3/api-reference/peripherals/gpio.html) and [board schematic](../research/ESP32-S3-ETH-Schematic.pdf).

## RP2350 connections

| RP2350 connection | Assigned use |
| --- | --- |
| GPIO16 UART0 TX | To ESP32 GPIO2 RX |
| GPIO17 UART0 RX | From ESP32 GPIO1 TX |
| Signal ground | Common reference for the short bench UART link |
| GPIO8 UART1 TX and GPIO9 UART1 RX | Onboard RS485 transceiver for client PC gateway |

The RP2350 UART header TX/RX are GPIO16/17, not GPIO0/1. Its header supply is jumper-selectable; avoid treating that power pin as a fixed 3.3 V logic reference. Use the [RP2350 schematic](../research/RP2350-Touch-LCD-7.pdf) to confirm the physical connector before wiring.

## Proposed I2C expansion

All addresses below are 7-bit addresses on ESP32 GPIO18/38. Device selection and supporting circuits remain proposed.

| Device | Address | Function | Design condition |
| --- | --- | --- | --- |
| MCP23017 | 0x20 | Slow digital inputs and outputs | GPA7 and GPB7 are output-only in the current datasheet |
| ADS1115 | 0x48 | Two proposed temperature channels, two provisional spare single-ended channels | Sensor excitation, conditioning and calibration still required |
| DS3231 | 0x68 | Battery-backed date and time | Backup supply and battery circuit required |
| Optional SC16IS752 | 0x4D | Additional UARTs if required | A1 and A0 tied to ground; optional, no IRQ GPIO allocated |

The SC16IS752 address table uses an 8-bit address notation: 0x9A corresponds to 7-bit 0x4D. Its optional polling strategy, bus load, and baud rates need verification. Do not accidentally select an address that conflicts with the ADC. RS232 or RS485 still requires a physical-layer transceiver.

### MCP23017 allocation

| Port pins | Proposed use |
| --- | --- |
| GPA0–GPA6 | Seven slow inputs, provisionally available for service key, auxiliary status, and possible rotor identification |
| GPA7 | Spare output |
| GPB0 | Active buzzer control through driver |
| GPB1 | Run lamp through driver |
| GPB2 | Alarm lamp through driver |
| GPB3 | Fan request through driver |
| GPB4 | Cooling request through driver |
| GPB5 | USB VBUS switch enable |
| GPB6–GPB7 | Spare outputs |

Input use within GPA0–GPA6 is not yet frozen. Four-bit rotor identification is only a possibility; a serial or RFID reader would change the interface requirement. Essential interlocks and overspeed capture are not assigned to this polled expander. Output drivers and hardware default states must remain inactive during startup, reset, or loss of communication.

The ADS1115 is a slow measurement ADC, with a maximum aggregate rate of 860 samples/s. It is not allocated for vibration waveform analysis, nor is it a complete direct interface for arbitrary RTDs or thermocouples. A digital imbalance switch was assumed in the GPIO count.

## Electrical and system work remaining

- Condition field inputs for their actual voltages, noise, open-circuit faults, and signal rates. Do not connect industrial field voltages directly to GPIOs.
- Select actuator drivers, isolation, suppression, and safe default states from the actual loads.
- Add the motor RS485 transceiver, termination/bias arrangement, connector, and protection after the motor interface is confirmed.
- Design USB host VBUS power switching, current protection, and connector routing; prevent accidental connection of a powered host arrangement to a PC.
- Define independent drive inhibition and safe lid release. Tach signal absence alone does not establish standstill.
- Establish I2C reset behavior and bus fault recovery without allowing a loss of expansion communication to create an unsafe output state.
- Verify all required tasks concurrently, including motor communication, sensor capture, Ethernet, WiFi, SD logging, and USB report export.

## Cross check status

The earlier allocation check found 15 unique GPIOs, all present on the header, with no overlap against the excluded flash/PSRAM, strapping, USB, LED, SD, and Ethernet pins. The proposed I2C addresses are distinct. These checks establish internal consistency of this allocation only. Physical wiring, firmware timing, electrical limits, complete peripheral coverage, and product safety are not yet validated.

Use the [open decisions in the project overview](../README.md#information-required-before-the-hardware-is-frozen) to complete the next revision.