# Centrifuge control electronics project

Saved on 19 October 2026 from the project discussion. The selected display is the **Waveshare RP2350-Touch-LCD-7**. The proposed application controller is the **Waveshare ESP32-S3-ETH standard board, SKU 28972**, with a custom interface carrier. The separate motor board handles motor drive and speed regulation only; the new electronics must manage the centrifuge.

The latest user-supplied I/O list includes two separate RS485 links for the display and VFD, Datasoft communication over Ethernet or Wi-Fi, tacho and Hall pulse inputs, RTD acquisition, I2C parameter memory and RTCC, and one Winbond NOR flash device. On the proposed board, use its existing W25Q128 as that single NOR device. These requirements supersede the earlier pin allocation; a complete assignment is still required. This is a design record, not a released schematic or a hardware validation result.

## Project files

| File | Contents |
| --- | --- |
| [Architecture](docs/architecture.md) | Board responsibilities, communication paths, and integration conditions |
| [I/O requirements](docs/io-requirements.md) | Current user-supplied interfaces, resource implications, and missing details |
| [Pin assignment](docs/pin-assignment.md) | Superseded allocation, board reservations, and revision status |
| [GPIO allocation](data/gpio-assignment.csv) | Earlier allocation with vendor header positions; superseded by the new I/O requirements |
| [Reserved pins](data/reserved-pins.csv) | Onboard uses and GPIO restrictions |
| [I2C devices](data/i2c-devices.csv) | Earlier candidate devices; revised RTD and parameter-memory selections remain open |
| [Client requirements](data/client-requirements.csv) | Original 24-item email summary; row 6 PC serial requirement/proposal is superseded by Datasoft over Ethernet or Wi-Fi |
| [Procurement snapshot](docs/procurement.md) | Earlier price and availability checks, with supplier links |
| [Sources](docs/sources.md) | Technical source URLs and local schematic copies |
| [Presentation](presentation/centrifuge-architecture.html) | Current five-view interactive architecture presentation; standalone HTML/CSS/JavaScript |
| [Presentation guide](presentation/README.md) | Local preview, controls, reading mode, and print instructions |
| [Archived presentation](presentation/archive/centrifuge-architecture-original-2026-10-19.html) | Original 15-slide discussion retained for reference |

The interactive presentation follows the current architecture and I/O requirements. The archived presentation and allocation CSVs preserve the earlier discussion. No replacement GPIO map has been frozen.

## Current decisions

- **User selected:** RP2350 touch display.
- **Recommended application controller:** ESP32-S3-ETH standard board without camera or PoE accessories for the bench POC.
- **Confirmed responsibility:** the separate motor controller provides drive and speed control; it does not own the complete centrifuge sequence.
- **User-identified machine I/O:** lid status and imbalance inputs, lid-lock solenoid output, tacho pulse input, and Hall pulse input for two-magnet rotor identification.
- **User-identified peripheral interfaces:** RTD through a 16-bit I2C ADC, external I2C parameter memory, I2C RTCC, one Winbond NOR flash device, Ethernet, USB, and two separate RS485 ports for the display and VFD. Datasoft communicates over Ethernet or Wi-Fi and needs no RS485 port.
- **NOR implementation on the proposed board:** use the existing 16 MB W25Q128 for firmware and allocated data storage; no second NOR chip is planned.
- **Proposed carrier work:** signal conditioning and drivers as needed, two ESP32-side RS485 transceivers, measurement and parameter-memory interfaces, clock backup, and protected USB host power. Existing motor-board circuitry must be checked before duplicating functions.

## Information required before the hardware is frozen

1. VFD model, RS485 protocol, run/stop and speed-reference command mapping, fault feedback, and communication-loss/drive-inhibition behavior.
2. Complete sensor and actuator inventory, quantities, voltage levels, signal types, and cable lengths.
3. Lid lock mechanism, feedback contacts, power loss behavior, and independent conditions for safe release.
4. Hall magnet pattern, timing tolerances, identification speed, and permitted speed limits per rotor.
5. Refrigeration, fan, compressor, valve, brake, and temperature sensor requirements, if applicable.
6. Display RS485 protocol and Datasoft application protocol, network configuration, access permissions, and reconnect behavior over Ethernet or Wi-Fi.
7. Independent protection architecture and the actual application safety requirements.
8. Firmware/data partition sizes on the single NOR device, whether microSD remains required, and storage capacity/endurance targets.
9. RTD type/channel count, ADC and parameter-memory parts, I2C addresses, and backup-clock requirements.

## Verification status

The earlier schematic and pinout review covered the superseded allocation only. Two directly connected RS485 ports consume two of the three ESP32-S3 UARTs. With conventional direction control, the identified interfaces require 13 application GPIOs against the earlier 15 suitable exposed pins, leaving two before debug and additional supporting controls. A complete pin assignment is still required before freezing a map. Firmware concurrency, electrical behavior, sensor performance, USB export, machine safety, and EMC remain to be demonstrated on hardware.

The archived presentation and research assets retain the earlier source material. Procurement figures are archived observations from 19 October 2026 and were not refreshed when this folder was created.